Chip mount, methods of making same and methods for mounting chips thereon

ABSTRACT

The present invention describes a pre-fabricated chip mount and a method for making the pre-fabricated mount. The mount includes a mount body and a protective ring attached to the body by a plurality of tabs. The mount also includes a plurality of inner leads in electrical communication with the wires of at least one leadframe and a receiving area for an integrated circuit chip. The present invention also describes chips mounted on the pre-fabricated mount and methods for mounting, wire-bonding and encapsulating the chip in the mount. The mounts of the present invention can also be adapted to accommodate multiple chips and multi-level bonding schemes to the chips.

RELATED APPLICATIONS

This application is a divisional U.S. patent application Ser. No.10/140,358, filed May 6, 2002, now U.S. Pat. No. 7,339,797 issued Mar.4, 2008 which is a continuation of U.S. patent application Ser. No.09/617,075, filed 17 Jul. 2000, now abandoned, which is a continuationof U.S. patent application Ser. No. 08/964,531, filed 5 Nov. 1997, nowabandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a chip mount, a method for making the chipmount and a method for mounting the chip on the chip mount.

More particularly, the present invention relates to a chip mount havinga designated chip flag area and configured so that at least one chip canbe directly bonded to at least one flag area, wire bonded to the leadsof at least one leadframe contained in the mount and encapsulated on themount where the mount is substantially pre-fabricated so that the chipis exposed to only a limited number of post-mounting manufacturingsteps.

2. Description of the Related Art

Integrated circuit dies or chips are subject to damage if not protectedby some type of casing or packaging. Current integrated circuit chippackaging involves mounting the chip or integrated circuit device on aleadframe substraight material with an adhesive agent and assembling achip mount around the attached chip.

Plastic packaging is one such method to protect fragile IC chips. Atypical IC packaging process includes mounting an IC die on a leadframeflag area using a suitable adhesive. The IC die and the leadframe arewire bonded. The IC die and the wire bonded leadframe are encapsulatedwith plastic leaving the leads of the lead frame exposed. The moldedframe then undergoes cleaning, which removes excess plastic from theouter leads, package body, and outer leadframe. The molded frame is thencured and the exposed leads are plated. Next, the dambars are cut andthe outer leads are cut away from the outer portion of the frame andthen formed into the desired shape

Such plastic packaging processes subject the chip to damage at everystep of the mounting manufacturing process which requires the scrappingof valuable IC die. Thus there is a need in the art for pre-fabricatedmounts and methods of utilizing pre-fabricated mounts to reduce thenumber of steps that integrated circuit chip must endure during themounting process.

SUMMARY OF THE INVENTION

This invention provides a chip mount including: a mount body; at leastone flag area designed to receive a chip and located in the top orbottom surface of the mount body; and a plurality of leads electricallyinsulated one form the other and each lead having an exposed innerportion (inner lead) for electrical coupling to contacts on a chipassociated with each flag area and an exposed outer portion (outer lead)designed for electrical coupling to external devices and designed toremain exposed after chip mounting. The chip mount can also include aprotection device for protecting the outer leads during chip mountingsuch as a protective ring connected to the body by a plurality ofbridges defining a plurality of hollow areas into which the outer leadscan extend.

This invention also provides a chip mounted including a chip attached(generally adhesively attached) to each flag area of a mount asdescribed above, a plurality of wire bonds connecting a plurality ofcontacts on the chip to the inner leads of the mount, and a capencapsulating the bonded chip, the wire bonds and the inner leads toform a mounted chip where the outer leads remain exposed for electricalcoupling to external devices.

The present invention also provides a method for making the mountcomprising the step of pre-fabricating a mount comprising a mount body;at least one flag area designed to receive a chip; and a plurality ofleads extending from each flag area and each lead having an exposedinner lead portion and exposed outer lead portion. Again, the mount caninclude a protection device such as a ring connected to the mount bodyby a plurality of bridges defining a plurality of hollow areas designedto protect the outer leads and to allow the outer leads to be cut andformed.

The method can include the step of forming a mount body out of a curableelectrically insulating (non-conductive) material such as plastic, epoxyresin or other molding compositions commonly used in chip manufacturing.During molding, a plurality of leads are placed into the mount andpositioned therein so that inner leads are exposed and so that the leadsare electrically insulated one from the other. At least one flag area,designed to receive a chip, is formed so that the inner leads areexposed and located at or near an edge of each flag area.

This invention also provides a method for mounting a chip includingaffixing or bonding (generally adhesively bonding) a chip onto each flagarea of a mount of the present invention; forming a plurality ofelectrical connections between a plurality of contacts on the chip and aplurality of the inner leads associated with each flag area of themount; and encapsulating, encasing or embedding the chip, theconnections and the inner leads in plastic or other non-conductivematerial, commonly used to make mounted chips to protect the chip, theinner leads and the connections. The method can also include removing aprotective device such as a ring and attachment bridges to produce amounted chip ready for installation. The method can optionally includecleaning and/or deflashing steps to clean the mount of excess moldcompound or encapsulation compound and to shape and size the mount.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be better understood with reference to the followingdetailed description together with the appended drawings in which likeelements are numbered the same:

FIG. 1A is a cross sectional view of a completed chip mount;

FIG. 1B is a cross sectional view of a completed chip mount having twoflag areas on the same surface of the mount;

FIG. 1C is a cross sectional view of a completed chip mount having twoflag areas on opposite surfaces of the mount;

FIG. 2 is a top view of a completed chip mount;

FIG. 3 cross sectional view of a complete chip mount showing mountedchip;

FIG. 4 is a fully completed chip mount package ready to be mounted;

FIG. 5A cross sectional view of a multi leadframe chip mount; and

FIG. 5B cross sectional view of a multi leadframe chip mount having twoflag areas on the same surface of the mount;

FIG. 5C cross sectional view of a multi leadframe chip mount having twoflag areas on opposite surfaces of the mount; and

FIG. 6 cross sectional view of a multi leadframe chip mount showingprotective ring.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The inventor has found that an improved procedure for mounting chips canbe implemented which will reduce the discard rate of mounting integratedcircuit devices by reducing the number of processing steps theintegrated circuit chip is subjected to during mounting.

This invention relates to a chip mount including: a mount body; at leastone flag area designed to receive a chip and located on a top or bottomsurface of the mount body; and a plurality of leads extending outwardfrom each flag area. The leads include an inner portion sometimesreferred to as the inner leads located at or near each flag areadesigned for electrical coupling to contacts on the chip or IC deviceand an outer portion sometimes referred to as the outer leads forelectrically coupling to external devices such as printed circuits. Theplurality of leads can be a leadframe or a plurality of leadframes.

Additionally, the mount can include a protective device to protect theouter leads and the chip once mounted and to provide the portion themount that is handled by the processing equipment. The protective deviceassociated with or connected to the mount body, which may be a ring,generally includes or defines a plurality of hollow areas into which theouter leads may extend to be accessible for subsequent processing. Theprotective device is generally removed after chip mounting.

This invention also provides amounted chip including a chip adhesivelyattached to each flag area of the mount described above, a plurality ofwire bonds connecting a plurality of contacts on the chip to the innerleads, and a cap encapsulating the adhesively bonded chip, the innerleads and the wire bonds so that the outer lead remain exposed forforming electrical contacts with external devices.

This invention also provides a method for making the mount comprisingthe steps of: forming a pre-mount including: a mount body; at least oneflag area designed to receive a chip and located in a top or bottomsurface of the mount body; and a plurality of leads embedded or encasedin the mount so that inner leads are exposed at or near an edge of eachflag area and a plurality of outer leads are exposed at or near an edgeof the mount body. Generally, the plurality of leads is part of aleadframe, but other lead systems can also be used. The mount can alsoinclude a mount protection ring designed to protect the mount body andouter leads during post-formation processing connected to the body by aplurality of bridges and defining a plurality of hollow areas into whichthe outer leads can extend to be trimmed, formed, and made accessible toexternal devices.

This invention also provides a method for mounting a chip comprising thesteps of: bonding a chip to each flag area of a pre-fabricated mount ofthe present; forming a plurality electrical connections between aplurality of contacts on the chip and a plurality of the inner leads;and encapsulating or encasing the chip, the inner leads and theconnections in a plastic or other non-conductive material to protect thechip and the connections. Additionally, the method can include removingthe protective device and cleaning or deflashing the mounted chip.

Generally, the chip mount of the present invention is composed of aleadframe or frames that have been encapsulated in a type of moldcompound. There is also a flag area formed into the mold compound wherethe IC die, chip or device will be attached to the preformed mount. Ifthe flag area includes electronic circuitry, then a metallic base can beadhered to or integrated with the flag area or adhered to or integratedwith the IC die before die bonding.

The mold compound can also be molded to form a protective device such asa protective ring around the chip mount adapted to hold the chip mountin place and to protect the outer leads and mount body from beingdamaged during subsequent processing. The protective ring can alsodefine hollow areas into which the outer leads can extend making themaccessible in order to remove the dambars and to form the leads into adesired shape. Because typical leadframes are constructed as a stripwith more than one leadsystem per strip, the protective rings of thepresent invention can also be connected together in a string so that theleadframe strips can be continuously set down into the protective ringsduring molding.

Generally, the procedure for making the chip mount of the presentinvention involves encapsulating only the leadframe in a plasticmaterial. The encapsulated leadframe can then be deflashed or cleaned ofexcess mold material to expose and clean the inner leads and the outerleads of the mount. The cleaned mount is then cured. Optionally, theinner leads and the outer leads can be plated; the dambar can be cutfrom between the outer leads; and forming the outer leads of the chipmount into a desired shape. It is understood that plating can be done atany of the preceding steps or at the very end of the process, and thatcleaning could occur several times after any of the preceding steps.

The encapsulated or molded plurality of lead such as a leadframe forms apartially completed chip mount. The areas that are molded are the chipreceiving areas (flag areas) so that the inner leads are at or near anedge of each flag area. Preferably, a protective ring is formed from theencapsulating material which extends outwards from the chip. Dambarsleave the outer leads void of molding compound. The die sections of themold press clamp and seal against the leadframe and the dambars tocreate cavities or hollow areas with no mold.

The partially completed chip mount and protective ring can now proceedthrough deflash where unneeded or excess plastic or mold compound iscleaned from the chip mount and protective ring. Deflashing can alsomake the chip mount an exact height which allows control over the mountbodies dimensions, the protective right dimensions and the inner leadsbonding heights.

After the chip mount mold compound has cured, the outer lead can be cutand formed. It is understood that the curing could have occurred beforeor after deflash. Now only the framing portion of the leadframe remainmolded within a protective ring attached to the chip mount with bridgesthat form hollow spaces in to which the outer leads can protrude. Theouter leads can then be formed into a desired shape because the moldcompound has encapsulated the inner lead holding the leads in place,while leaving the inner leads exposed so that the inner leads can bebrought into electrical contact with contacts on the chip.

If required, the inner leads and/or the outer leads can be plated. Ifplating is required, the leadframe will preferably remain intact beforethe leads are trimmed and formed.

The chip mount must be cleaned. The cleaning can be done after mold cureand before plating. It is important that the chip mount be completelyvoid of all contaminants before the IC die is exposed to the chip mount.After cleaning, an IC chip is mounted onto each flag area of the chipmount with any suitable adhesive agent.

Generally, the procedure for attaching an IC die to the chip mountincludes mounting the IC die or chip onto the flag area of thepre-molded chip mount; wire bonding contacts on the IC die to the innerleads of the mount body; encapsulating the IC die, the inner leads andwire bonded leads in a plastic or other non-conductive material; andtrimming the finished molded device from the protective ring to form afinished mounted IC die or chip product such as a mountable memory chipor processor chip.

Electrical connections between the contacts or contact areas on the ICchip and the inner leads of the chip mount are preferably accomplishedby bonding wires from the IC chip bonding pads, contacts or contactareas to the proper inner leads. There are several well known wirebonding methods that can be implemented. Important considerationsinclude the following: the amount of heat the mold compound can absorbbefore reaching its glassing point; how much heat the IC chip canwithstand before damage occurs; and the nature of the material beingused for the wire bonding and/or the inner leads such gold, tin,aluminum, etc. Although wire bonding is preferred any other bondingtechnique can be used provided that the bonding pad and contacts on theIC chip are place in electrical communication with the desired innerleads.

The IC die and wire bonded inner leads are then encapsulated withplastic which embeds the flag areas, the IC chip, the wire bonds, theinner leads and a portion of the mount past the inner leads. There aregenerally two methods to encapsulate the exposed IC chip and wires. Thefirst method involves encapsulating the IC chip on the chip mount withplastic, glass, epoxy, or some other nonconductive material that wouldprotect the IC chip from contamination. The encapsulated chip mount isthen preferably capped with a cover plate. The second method involvesencapsulating the IC chip in molding compound in a mold press. Theencapsulated frame and IC die are then cleaned of any excess plastic ormolding compound, the plastic or compound is then cured and the finisheddevice is cut from the protective ring.

The pre-molded package with the protective ring has several advantages.The pre-molded package can be surfaced to a specific level, making thebonding heights of the inner leads more consistent, thus accommodatingthe equipment used to produce IC packaging. The outer dimensions andsize of the protective ring are also important for machine handling aslarger sizes provide more support than a fragile metal leadframe. Thedesign layout is also more flexible because lead counts can be increasedby simply using more than one leadframe in the mount body. This latterarrangement will eliminate the need for more complex leadframes.Moreover, the new process will only expose the IC die or chip to theplastic packaging process during the steps of: die bonding, wirebonding, mold encapsulating and deflashing. These four process stepgenerally have very low scrap rates as opposed to current processingwhere the majority of scrapping of IC dies and chips occurs in plating,singulating, trimming and forming.

Referring now to FIGS. 1 and 2, amount 10 includes amount body 12 havinga top surface 14 and a bottom surface 16. The top surface 14 of themount body 12 includes at least one area 18 designed to receive anintegrated circuit chip 20 (shown in phantom in FIG. 1A). The area 18 issometimes reference to herein as a flag area. The flag area 18 ispreferably recessed into the top surface 14 of the mount body 12 so thata top 22 of the chip or die 20 is either below (as shown) orsubstantially co-planar with the top surface 14 of the mount body 12.However, it should be understood that the flag area 18 can be below,co-planar, or above the top surface 14 depending on the design of thefinal product.

Embedded in the top surface 14 of the mount body 12 and extending froman edge 24 of the recessed flag area 18 toward a plurality of hollowareas 26 is a plurality of leads 40. Each lead 40 includes a first end28 sometimes referred to as lead finger or inner lead. The inner leads28 are designed to be brought into electrically connected to or inelectrical communication with contacts 34 (shown in FIG. 3) on the chip20. Of course, each inner lead 28 can be either connected or unconnectedto a chip contact depending on the chip design and/or the leadframedesign. Each lead 40 also includes a second end 42 sometime referred toas the outer leads extending into the plurality of hollow areas 26 anddesigned to be brought into electrical contact or communication withexternal devices such as printed circuit boards or other externaldevices well-known in the art.

The mount body 12 is generally protected by a protective ring 44 whichis attached to the mount body 12 by a plurality of tabs 46. The tabs 46are designed to be cut once the entire chip mounting process iscomplete. Removing the protective ring 44 and the tabs 46 exposes theouter leads 42 of the leads 40 so that the mounted chip can now be usedin the manufacture of printed circuit or similar devices. Althoughprotective rings are one method of protecting the out leads during chipmounting and encasing steps, other protecting devices can be used aswell. Such other protection could include reusable holders which retainthe mount, provide access to the flag areas for chip mounting, provideaccess to the inner lead and the chip contacts for wire bonding, provideaccess to the mounted chip and wire bonds for encasement and protect theouter leads from damage during chip mounting. Such devices wouldgenerally hold the mount at its four corners or the mount could includespecially designed and optionally removable holding tabs or raisedportions.

Referring now to FIG. 1B, a mount 10 includes a mount body 12 having atop surface 14 and a bottom surface 16. The top surface 14 of the mountbody 12 includes two flag areas 18 a&b designed to receive integratedcircuit chips 20 a&b (shown in phantom in FIG. 1B). The flag areas 18a&b are preferably recessed into the top surface 14 of the mount body 12so that tops 22 a&b of the chips or dies 20 a&b are either below (asshown) or substantially co-planar with the top surface 14 of the mountbody 12. However, it should be understood that the flag areas 18 a&b canbe below, co-planar, or above the top surface 14 depending on the designof the final product.

Embedded in the top surface 14 of the mount body 12 and extending fromouter edges 24 o of the recessed flag areas 18 a&b toward a plurality ofhollow areas 26 is a plurality of outer leads 40 o. Each outer lead 40 oincludes a first end 28 o. The first ends 28 o are designed to bebrought into electrically connected to or in electrical communicationwith contacts 34 (similar to those shown in FIG. 3) on the chips 20 a&b.Of course, each first end 28 can be either connected or unconnected to achip contact depending on the chip design and/or the leadframe design.Each outer lead 40 o also includes a second end 42 o sometime referredto as the outer leads extending into the plurality of hollow areas 26and designed to be brought into electrical contact or communication withexternal devices such as printed circuit boards or other externaldevices well-known in the art. Also embedded in the top surface 14 ofthe mount body 12 and extending from inner edges 24 i of the recessedflag areas 18 a&d to below the bottom surface 16 of the body 12 endingin a plurality of inner leads 40 i having first inner lead ends 28 i andsecond inner lead ends 42 i.

The mount body 12 is generally protected by a protective ring 44 whichis attached to the mount body 12 by a plurality of tabs 46. The tabs 46are designed to be cut once the entire chip mounting process iscomplete. Removing the protective ring 44 and the tabs 46 exposes theouter leads 42 i&o of the leads 40 i&o so that the mounted chip can nowbe used in the manufacture of printed circuit or similar devices.Although protective rings are one method of protecting the out leadsduring chip mounting and encasing steps, other protecting devices can beused as well. Such other protection could include reusable holders whichretain the mount, provide access to the flag areas for chip mounting,provide access to the inner lead and the chip contacts for wire bondingprovide access to the mounted chip and wire bonds for encasement andprotect the outer leads from damage during chip mounting. Such deviceswould generally hold the mount at its four corners or the mount couldinclude specially designed and optionally removable holding tabs orraised portions.

Referring now to FIG. 1C, a mount 10 includes a mount body 12 having atop surface 14 and a bottom surface 16. The top surface 14 and thebottom surface 16 of the mount body 12 include flag areas 18 a&bdesigned to receive integrated circuit chips 20 a&b (shown in phantom inFIG. 1C). The areas 18 a&b is sometimes reference to herein as a flagarea. The flag areas 18 a&b are preferably recessed into the top surface14 and the bottom surface 16 of the mount body 12 so that tops 22 a&b ofthe chips or dies 20 a&b are either below (as shown) or substantiallyco-planar with the top surface 14 or bottom surface 16 of the mount body12. However, it should be understood that the flag areas 18 a&b can bebelow, co-planar, or above the top surface 14 and bottom surface 16depending on the design of the final product.

Embedded in the top surface 14 and the bottom surface 16 of the mountbody 12 and extending from an edge 24 of the recessed flag areas 18 a&btoward a plurality of hollow areas 26 is a plurality of top leads 40 tand a plurality of bottom leads 40 b. Each lead 40 t or 40 b includes afirst end 28 t or 28 b, respectively, sometimes referred to as leadfinger or inner lead. The inner leads 28 t&b are designed to be broughtinto electrically connected to or in electrical communication withcontacts 34 (similar to those shown in FIG. 3) on the chips 20 a&b. Ofcourse, each inner lead 28 t&b can be either connected or unconnected toa chip contact depending on the chip design and/or the leadframe design.Each lead 40 t&b also includes a second end 42 t&b sometime referred toas the outer leads extending into the plurality of hollow areas 26 anddesigned to be brought into electrical contact or communication withexternal devices such as printed circuit boards or other externaldevices well-known in the art.

The mount body 12 is generally protected by a protective ring 44 whichis attached to the mount body 12 by a plurality of tabs 46. The tabs 46are designed to be cut once the entire chip mounting process iscomplete. Removing the protective ring 44 and the tabs 46 exposes theouter leads 42 t&b of the leads 40 t&b so that the mounted chip can nowbe used in the manufacture of printed circuit or similar devices.Although protective rings are one method of protecting the out leadsduring chip mounting and encasing steps, other protecting devices can beused as well. Such other protection could include reusable holders whichretain the mount, provide access to the flag areas for chip mounting,provide access to the inner lead and the chip contacts for wire bonding,provide access to the mounted chip and wire bonds for encasement andprotect the outer leads from damage during chip mounting. Such deviceswould generally hold the mount at its four corners or the mount couldinclude specially designed and optionally removable holding tabs orraised portions.

Referring additionally now to FIGS. 3 and 4, once the mount 10 has beenprefabricated, the integrated circuit chip 20 can be set into the flagarea 18 and adhesively bonded in place as shown in FIG. 3. The adhesiveis then generally cured so that the bond is secure. The adhesive isgenerally an epoxy resin; however, any other adhesive can be used aswell, provided that the adhesive bonds the chip to the mount and doesnot adversely affect chip performance. With the chip 20 secured inplace, chip contacts 34 are brought into electrical communication withthe inner leads 28 of the leads 40 by wire bonds 48. The layout andnumber of wire bonds 48 will depend on the chip and/or leadframe designand the chips ultimate use. The mount 10 can support any number ofwiring schemes including multi-level wiring schemes.

After wire bonding has been completed and checked, the chip 20, the wirebonds 48 the inner leads 28 are encapsulated in a plastic material toform a cap 53 which yields a final mounted chip. Only the outer leads 42of leads 40 are not encapsulated in the plastic material and extend outfrom the mounted chip. These outer leads 42 provide the electricalcommunication pathways into and out of the chip 20.

Besides single level wire bonding as shown in FIGS. 1-4, the presentinvention also easily supports multi-level wire bonding for higher pinnumbers. By multi-level wire bonding, the inventor means that the mount10 can incorporated more than one leadframe or its equivalent. Theinclusion of more than one leadframe or other similar lead format allowsthe final product to have many more electrical communication pathwaysinto and out of the mounted chip. Such multi-level bonding scheme canalso be used to package more than one integrated circuit chip into asingle mount. Thus, a multi-level mount could support a centralprocessing unit and a cache memory module or logic chips.

The bonding scheme between the chip contacts and the inner leads whichwill be exposed would include connections to the appropriate CPUcontacts with the cache memory module and allow the cache and CPU tohave independent electrical communication pathways to the outside world.Thus, the final product would support cache module communication with amain memory module or any chip combination, while the CPU would beconnected with other hardware modules. Other multi-chip and multi-levelmount designs can be used as well limited only by physical space andhuman ingenuity.

Referring now to FIGS. 5A and 6, one such multi-level mount 100 is shownto include a mount body 102, a bottom plurality of leads 104, a topplurality of leads 106 having a bump 128 designed to allow theencapsulating material to encapsulate an inner part 124 of the leads 106and leave an outer part 126 of the leads 106 exposed, and an insulatinglayer 108 interposed therebetween. The mount 100 also includes at leastone chip mount area 110, preferably recessed in the mount body 102. Themount 100 is shown with a chip 112 mounted adhesively in the area 110.One set of chip contacts 114 are bonded to the bottom plurality of leads104 by wire bonds 116, while a second set of chip contacts 118 arebonded to the top plurality of leads 106 at the inner parts 124 by wirebonds 120 as shown in FIG. 5A. The mounting system shown in FIGS. 5-6 issometimes referred to as a surface mounting system. Such mountingsystems can then be combined with other wiring systems and manufacturingtechniques to form multi-chip devices or to be combined with other wirebonding systems to form completed devices.

Referring now to FIG. 5B, one such multi-level mount 100 is shown toinclude a mount body 102, two plurality of bottom leads 104 a&b, twoplurality of top leads 106 a&b, and insulating layers 108 interposedtherebetween. The top leads 106 a include bumps 128 a&b designed toallow the encapsulating material to encapsulate inner parts 124 a&b ofthe top leads 106 a&b and leave outer parts 126 a&b of the top leads 106a&b exposed. The mount 100 also includes two chip mount areas 110 a&b,preferably recessed in the mount body 102. The mount 100 is shown withtwo chips 112 a&b mounted adhesively in the areas 110 a&b. Chip contacts114 a&b are bonded to the bottom plurality of leads 104 a&b by wirebonds 116 a&b, while chip contacts 118 a&b are bonded to the topplurality of leads 106 a&b at the inner parts 124 a&b by wire bonds 120a&b as shown in FIG. 5B. The mounting system shown in FIGS. 5-6 issometimes referred to as a surface mounting system. Such mountingsystems can then be combined with other wiring systems and manufacturingtechniques to form multi-chip devices or to be combined with other wirebonding systems to form completed devices.

Referring now to FIG. 5C, one such multi-level mount 100 is shown toinclude a mount body 102, a bottom plurality of leads 104 a&b, a topplurality of leads 106 a&b having bumps 128 a&b designed to allow theencapsulating material to encapsulate inner parts 124 a&b of the topleads 106 a&b and leave outer parts 126 a&b of the top leads 106 a&bexposed, and an insulating layer 108 interposed therebetween. The mount100 also includes two chip mount areas 110 a&b, preferably recessed inthe mount body 102 and one on a top side 103 a of the mount 102 and oneon a bottom side 103 b of the mount 102. The mount 100 is shown with twochips 112 a&b mounted adhesively in the areas 110 a&b. Chip contacts 114a&b are bonded to the bottom plurality of leads 104 a&b by wire bonds116 a&b while chip contacts 118 a&b are bonded to the top plurality ofleads 106 a&b at the inner parts 124 a&b by wire bonds 120 a&b as shownin FIG. 5C. The mounting system shown in FIGS. 5-6 is sometimes referredto as a surface mounting system. Such mounting systems can then becombined with other wiring systems and manufacturing techniques to formmulti-chip devices or to be combined with other wire bonding systems toform completed devices.

Alternatively, the mount 100 the surface leads 104 and 106 can bereplaced by other type of lead systems such as the leadframes of FIGS.1-4. Again, the lead systems would include inner lead portions to beelectrically coupled to contacts on the chip and outer lead portions tobe electrically coupled to external devices. If the mount 100 includesleadframes instead of a surface mounting system, then the outer leads ofthe leadframes will extend into a plurality of hollow areas 134. Again,the hollow areas 134 are defined by the mount body 102 and a protectivering 136 and a plurality of connecting tabs 138 connecting theprotective ring 136 to the mount body 102.

The mounts of the present invention are manufactured as a unit ofmaterials generally used to make integrated circuit mounts such ascurable plastic material as is well-known in the art as furtherdescribed in U.S. Pat. Nos. 5,106,784, 4,607,276 and 4,303,934,incorporated herein by reference. The mount body is generally made withthe leadframe and its leads, which are combined during molding. Theleadframes and the inner leads are set in place and are molded togetherand thermally cured to set the chipmount. Excess plastic is cleaned fromthe mount containing the leadframe and the inner and outer leads.

The pre-fabricated mount incorporating at least one leadframe and a setof inner leads provides great flexibility to the chip designers. Thepre-fabricated mounts can be made with more than one level of leadframesto accommodate the ever increasing density of contacts on the chipsurface and the ever increasing number of contacts the chip needs to theoutside.

Although the invention has been disclosed with reference to itspreferred embodiments, from reading this description those of skill inthe art may appreciate changes and modification that may be made whichdo not depart from the scope and spirit of the invention as describedabove and claimed hereafter.

1. A pre-fabricated chip mount comprising: a. a mount body; b. aplurality of flag areas disposed in a top or bottom surface of the mountbody; c. a plurality of lead structures comprising bottom leads, topleads, and insulating layers interposed between corresponding top leadsand bottoms leads, one structure for each flag area, where each top leadinclude an inner part, an outer part and a bump adapted to allowencapsulating material to encapsulate the inner part leaving the outerpart exposed and where each bottom lead includes an inner part adaptedto be encapsulated by the encapsulating material and an outer exposedpart, and where each flag area is designed to receive a chip and wirebonds bonding chip contacts to corresponding inner parts of the topleads and bottom leads of the lead structure associated with the flagarea and where the pre-fabricated chip mount is designed to have eachflag area, the chips, the wire bonds, the inner parts of the top andbottom leads and a portion of the mount body between the bumps on thetop leads embedded in a nonconductive material.
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 25. The mount of claim 1,wherein the leads comprise a plurality of leadframes.
 26. The mount ofclaim 1, wherein the flag areas are located in a top surface of themount body.
 27. The mount of claim 26, wherein each flag area includes ametallic base onto which each chip is mounted and wherein each flag areais located in an indentation in the mount body.
 28. A mounted chipcomprising: a. a pre-fabricated chip mount including: i. mount body; ii.a plurality of flag areas disposed in a top or bottom surface of themount body; iii. a plurality of lead structures comprising bottom leads,top leads, and insulating layers interposed between corresponding topleads and bottoms leads, one structure for each flag area, where eachtop lead include an inner part, an outer part and a bump adapted toallow encapsulating material to encapsulate the inner part leaving theouter part exposed and where each bottom lead includes an inner partadapted to be encapsulated by the encapsulating material and an outerexposed part, b. a chip mounted in each flag area; c. a plurality ofelectrically conductive wire bonds connecting contacts on the chip tocorresponding inner parts of the top leads and bottom leads of the leadstructure associated with the flag area; and d. a cover comprising anonconductive material embedding the flag areas, the chips, the wirebonds, the inner parts of the top and bottom leads and a portion of themount body between the bumps on the top leads in the nonconductivematerial.
 29. The chip of claim 28, wherein the leads comprise aplurality of leadframes.
 30. The chip of claim 28, wherein the flagareas are located in a top surface of the mount body.
 31. The chip ofclaim 30, wherein each flag area includes a metallic base onto whicheach chip is mounted and wherein each flag area is located in anindentation in the mount body.
 32. The chip of claim 28, wherein theleads comprise a plurality of leadframes.
 33. The chip of claim 28,wherein each flag area includes a metallic base onto which each chip ismounted and wherein each flag area is located in an indentation in themount body.